1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a method of manufacturing contacts and metal interconnections in the cell and peripheral circuit areas of a nonvolatile semiconductor memory device.
2. Description of the Related Art
A NAND-type flash memory is known as one of the nonvolatile semiconductor devices. The cell array of the NAND-type flash memory has cell transistors and select gate transistors. In many cases, a peripheral circuit required for the operation of the memory is formed on a single substrate together with a memory cell array.
The gate electrodes of the cell transistors and select gate transistors may be subjected to silicidation. The silicidation of the gate electrodes can lower the resistance between them and contact plugs. On the other hand, the gate electrode structures of transistors in the peripheral circuit area are not subjected to silicidation when they are used as high-resistance elements. This causes the following phenomena to occur depending on the manufacturing process.
The gate structure which is not subjected to silicidation is coated with a barrier layer. After the barrier layer has been formed to coat the gate electrodes and the gate structures in the memory cell area and the peripheral circuit area, portions of the barrier layer which overlie the gate electrodes that are subjected to silicidation are removed. In removing the barrier layer, the interlayer insulating layer underlying the barrier layer is also etched partially because high selectivity cannot be adopted between the interlayer insulating layer and the barrier layer. As a result, the top of the interlayer insulating layer between the gate electrodes becomes much lower in level than the top of the gate structures.
After the silicidation process, a further interlayer insulating layer is deposited over the entire surface of the semiconductor substrate. At this point, depressions are formed in the upper-level interlayer insulating layer along the portions in the top of the lower-level interlayer insulating layer which have sunk. After that, interconnect trenches for bit lines are formed so as to cross the depressions and the depressions and the interconnect trenches are filled with conductive material. As a result, interconnect layers 103 are formed as shown in FIG. 27. At this point, a conductive material 102 buried in the previously formed depressions would electrically connect the interconnect layers 103 with one another.
The influence of steps in the underlying interlayer insulating layer 101 on the thickness of the interconnect layers 103 may cause variations in interconnect resistance. In FIG. 27, reference numeral 104 denotes a contact plug.
In order to prevent the interlayer insulating layer from being etched, one might suggest a high selectivity between the barrier layer and the underlying interlayer insulating layer. However, no combination of materials which meet the required functions of the interlayer insulating layer and the barrier layer and yet allow high selectivity therebetween has been realized up to date.